1. Field of the Invention
The invention relates to an integrated circuit for high frequency mixers and more particularly to dual gate cascode mixers in the Giga Hertz range.
2. Description of the Related Art
Noise figure is very often the most critical specification in most receiver networks. Another equally and increasingly important specification is the suppression of the intermodulation or IM products. IM3 or the third order intermodulation is the strongest of the odd harmonic spurious signals that are generated as shown in FIG. 1.
In FIG. 1, F1 and F2 denote signal at two frequencies. When the two signals are mixed, intermodulation (IM) frequencies are generated. FIG. 1 displays these IM frequencies as a function of power, in dBM. These IM frequency are the sums or differences of frequencies F1 and F2 or of their multiples. Third order intermodulation products are shown grouped around F1 and F2, while even order intermodulation products are shown spread in groups of three at some distance (frequency) at either side of F1 and F2.
Suppression of IM products is an area of important consideration in the receiver design of most transceiver networks because spurious signals can be misinterpreted as the desired signals. In an ideal situation one would want to suppress all IM signals, be they odd or even orders. One can effectively suppress the even order IM located at the low and high frequency end, by using matching networks as shown in FIG. 2.
FIG. 2 depicts a Receive Front End (RFE) 201. It has inputs RF-in, LO in, and output IF-out. RF-in feeds a downmixer 230 via a series of three match networks 210, interspersed with a Low Noise Amplifier 1 (LNA1) 211, and a Low Noise Amplifier 2 (LNA2) 212. Similarly, LO-in feeds downmixer 230 via a match network 210 followed by a LO Buffer 213, followed by another match network 210.
The intermodulation product 3 or IIP3 specifications for a Personal Handy Phone or PHS system is xe2x88x9218 dBm. IIP3 is a figure of merit that measures how well a circuit suppresses the third order IM3 signals. It is calculated by the following formula:                     IIP3        =                  Pin          +                      Delta            2                                              (        1        )            
Pin is the input power and Delta is the amount of suppression IM3 is from IM1 or the power at the fundamental frequency as shown in FIG. 1.
With the newer wireless communication system which results in increasingly denser communication traffic, this IIP3 specification is becoming ever more difficult to achieve. For example the newer system like the CDMA PCS, or Code Division Multiple Access Personal Communication System, operating at 1.9 GHz have a stringent IIP3 requirement of xe2x88x925 dbm.
In a receive front end (RFE) implementation as shown in FIG. 2, the downmixer is commonly the last block for the Microwave Monolithic Integrated Circuit (MMIC) down converter. This downmixer is commonly the implemented using the dual gate mixer topology as shown in FIG. 3. The mixer is designed as a cascode connected metal epitaxial field effect transistor (MESFET) with transistors M1 and M2 connected in series. The intermediate frequency (IF) is extracted from the drain (D2) of M2. With proper bias control at G1 and G2, a good conversion gain can be obtained. However, OIP3 of the dual gate mixer configuration is fixed even if the conversion gain of the mixer can be further increased. A new circuit topology is needed to address this bottleneck of the increase of OIP3 as is the case in the dual gate mixer. It will be difficult with the present MMIC dual gate configuration to meet the future demand in the third harmonic suppression.
We now provide a more detailed description of FIG. 3. The components of high frequency mixer circuit 301 consist of a radio frequency (RF) matching network 311, a buffer/interstage matching network 312, a dual-gate mixer, or downmixer, 315, and an output matching network 320. Network 312 is made up of a local oscillator (LO) buffer 313, followed by an Interstage matching network 314. Both network 311 and 312 are of conventional design. The RF matching network 311, with input RF-in, and the buffer/interstage matching network 312, with input LO-in, are used for suppression of even order intermodulation. The output of 311 and 312 feeds inputs G1 and G2 of dual-gate mixer 315, respectively. The dual-gate mixer frequency shifts the two input signals at G1 and G2 to an intermediate frequency (IF) signal. An output matching network 320, connected to the drain D2 of M2 and matches the impedance D2 to the impedance of output IF-out. Other inputs to the high frequency mixer circuit are a voltage supply and Ground.
Still referring to FIG. 3, the dual-gate mixer 315 consists essentially of two metal epitaxial field effect transistors (MESFET) M1 and M2 connected in a cascode manner where 311 and 314 set the DC bias for the gates of M1 and M2, respectively. Describing 315 now in greater detail, resistor R2, paralleled by capacitor C2, is connected at one end to Ground and at the other end to the source S1 of MESFET M1. The gate of M1 is connected to input G1. The drain of M1 is connected to the source of MESFET M2. The point between M1 and M2 is labeled X. The gate of M2 is connected to input G2. The drain D2 of M2 is connected to the output matching network 320.
Maas in his book (Stephen A. Maas, xe2x80x9cMicrowave Mixersxe2x80x9d, pp. 323-331, Second Edition, Artech House) provides a description of the principle behind the working of the dual gate FET as shown in FIG. 3. For optimum mixing to occur, the bottom MESFET M1 is biased near the border of the linear and saturation region for the MESFET. Therefore, as the LO signal is pumped into the gate of M2, the source follower effect allows the LO signal to affect the drain-to-source (Vds) of M1. This allows M1 to switch between the linear and saturation region and changes its transconductance and drain-to-source conductance. The resultant IF frequency is then amplified through the common gate amplifier effect of M2. With the large LO signal applied to M2, its performance is affected as a common gate amplifier for the IF signal.
U.S. Pat. No. 5,444,399 (Shiga) describes a pulse doped process MESFET which is more robust than the conventional MESFET in dealing with the problem described in the preceding paragraph. Shiga proposes a change in process such that the transconductance of the MESFET is flatter for a larger span for Vgs variation. This change implies fundamental process changes, however. U.S. Pat. No. 5,640,692 (Bothorel) discloses the addition of an attenuator before the mixer to provide a lower third order intermodulation suppression. U.S. Pat. No. 5,060,298 (Waugh et al.) provides a double balanced mixer with an active distributed balun, which results in a high third order intercept point. U.S. Pat. No. 4,949,398 (Maas) provides a GaAs MESFET mixer in which the resistive channel of the MESFET is used to approximate a time-varying liner resistor to improve intermodulation performance. U.S. Pat. No. 4,845,389 (Pyndiah, et al.) discloses a traditional dual gate mixer which adds an inductor at the junction point of the two transistors. U.S. Pat. No. 5,306,969 (Kimura) provides a dual-gate mixer in which the two FET""s have different transconductances.
It is an object of the present invention to provide a mixer circuit that will have a higher third order intermodulation suppression and a more robust conversion gain.
Another object of the present invention is to provide a circuit which eliminates external components, such as inductors to act as chokes.
A further object of the present invention is to provide a circuit which can be implemented in another field effect technology such as complimentary metal oxide semiconductor (CMOS) technology.
A yet further object of the present invention is to provide a circuit which can be modified into a double balanced structure or can be used as a frequency-up converter.
These objects have been achieved by providing a new downmixer coupled where the intermediate frequency (IF) is extracted at the midpoint between two metal epitaxial field effect transistors (MESFET) of the downmixer and by adding a common source mode IF amplifier which is coupled to that midpoint.